1. Field of the Invention
The present invention is directed to synchronizing a local clock relative to a reference clock that is supplied for synchronous data transfers, for example a PCI clock. More particularly, the present invention relates to use of digital phase shifting systems for outputting a phase-shifted signal that is synchronized relative to a reference clock.
2. Background Art
Newer communications systems require advanced processing of high speed digital signals in order to accommodate precise timing requirements. For example, processor-based communications systems use high-speed (e.g., 1.6 Gbits/sec and above) source synchronous data communications systems, such as HyperTransport™ bus architectures, and synchronous systems such as Peripheral Component Interconnect (PCI) bus systems.
Synchronous communications systems, such as PCI transmission systems, rely on a common time base for synchronization of local clocks of respective transmitting and receiving devices. For example, a PCI bus master device transmits data to a PCI bus slave device based on an external clock, typically which is supplied by an external source. Hence, the PCI bus master device is required to transmit data in a manner that is aligned relative to the external clock within a prescribed tolerance interval, and the receive device is required to latch the incoming data within a prescribed time interval relative to the external clock.
Existing PCI specifications have prescribed timing requirements between the reference clock and the transmission of transmit data. In particular, existing PCI specifications impose a requirement that valid transmit data be output within a prescribed time interval of the rising clock edge of the reference clock at the interface of the transmitter; in other words, transmitters have limited time constraints (having minimum and maximum time interval boundaries) from the rising edge of the clock to when the data must transition on the PCI bus. Hence, a transmitter needs to output valid data within about 3 nanoseconds of the rising edge of the reference clock; however, internal propagation delays within the integrated circuit of the transmitter may cause the delay between the rising edge of the reference clock, and the instance at which output data can be driven onto the bus, to be up to 6-8 nanoseconds. Hence, the phase of the clock used to transmit the data must be adjusted to be earlier than the reference clock.
The existing PCI specifications also specify that for the receiver, data that changes within a certain window about the rising edge of the reference clock must be sampled correctly by the receiving device (e.g., sampling and holding the data on the bus within 2-3 nanoseconds). Consequently, the transmitter and the receiver must follow stringent timing requirements.
Prior art devices have relied on an analog phase locked loop (PLL) to phase align their local clocks to the external clock. For example, the PLL typically includes a phase comparator that is used to directly compare a reference clock to a locally-generated clock signal, also referred to herein as the feedback clock signal: the phase comparator outputs a phase difference signal to a low pass filter, which outputs the filtered signal to a voltage controlled oscillator. The voltage controlled oscillator outputs a clock signal based on the phase difference signal to a buffer circuit. The buffer circuit outputs the feedback clock signal back to the phase comparator, and also outputs the feedback clock signal to output buffers configured for outputting respective data values onto a data bus synchronous with the feedback clock signal.
One particular disadvantage of prior art phase locked loops is that they are sensitive to the frequency of the reference clock; hence, PLLs tend to have a limited frequency range. However, newer PCI bus protocols require PCI bus circuitry to be able transmit over a reference clock frequency range of as low as 1 MHz or lower, to over 133 MHz, resulting in a frequency range of over one decade that cannot be readily accommodated by a conventional PLL. Such a large frequency range requires conventional PLLs to be modified to include feedback dividers that utilize different clock frequencies, resulting in additional sources for timing errors. Hence, the prior art phase locked loops require increased complexity in order to handle the wider frequency range.
In addition, attempts at deskewing (i.e., phase aligning) the transmitter and receiver becomes more difficult as the frequency of the signal increases, since the phase skew increases proportionally with an increase in the increase in frequency.
Another example of phase adjustment involves use of digital delay lines configured for locking to the incoming reference clock frequency, for example by delaying a locally-controlled signal by 90 percent of its cycle, i.e., to obtain an earlier clock edge. However, such digital delay lines when implemented using the requisite inverter have a resolution limited to about 50-60 picoseconds, resulting in the disadvantage of having a relatively low degree of precision, limited accuracy, and a limited frequency range. Consequently, digital delay lines have a limited ability to provide precise phase adjustments.
In addition, digital phase shifting systems in an integrated circuit often rely on binary coding, where a digital value composed of N bits has a range of values from zero to 2N−1. Reliance on binary coding suffers from the disadvantage of Most Significant Bit (MSB) rollover, where a simultaneous transition in multiple bits due to a change in value (e.g., “7”=0111 to “8”=1000) creates numerous discontinuities in the circuits implementing the digital system, resulting in voltage spikes that may cause transient phase errors on the output signal; such voltage spikes may cause transient phase errors that may result in misinterpretation of a clock strobe, data, etc., resulting in errors due to instability of the output signal. Efforts to filter the voltage spikes, or the transient phase errors, from the output signal often are not practical in integrated circuits due to the added delay or the increased capacitance.
In addition, implementation of digital phase shifting systems in an integrated circuit may encounter errors due to nonlinearities due to process variations encountered during manufacture of the integrated circuit.
Finally, digital phase shifting systems may suffer from the problem of adding a bias to the reference clock signal that may affect the duty cycle of the output signal.